LCOV - app.info - ipc/chromium/src/base/atomicops_internals_x86_gcc.cc

LCOV - code coverage report
| Current view: | directory - ipc/chromium/src/base - atomicops_internals_x86_gcc.cc (source / functions) |  | Found | Hit | Coverage |
| Test: | app.info | Lines: | 22 | 19 | 86.4 %
| Date: | 2012-07-07 | Functions: | 5 | 4 | 80.0 %

           1                 : // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved.
           2                 : // Use of this source code is governed by a BSD-style license that can be
           3                 : // found in the LICENSE file.
           4                 :
           5                 : // This module gets enough CPU information to optimize the
           6                 : // atomicops module on x86.
           7                 :
           8                 : #include <string.h>
           9                 :
          10                 : #include "base/atomicops.h"
          11                 : #include "base/basictypes.h"
          12                 :
          13                 : // This file only makes sense with atomicops_internals_x86_gcc.h -- it
          14                 : // depends on structs that are defined in that file.  If atomicops.h
          15                 : // doesn't sub-include that file, then we aren't needed, and shouldn't
          16                 : // try to do anything.
          17                 : #ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
          18                 :
          19                 : // Inline cpuid instruction.  In PIC compilations, %ebx contains the address
          20                 : // of the global offset table.  To avoid breaking such executables, this code
          21                 : // must preserve that register's value across cpuid instructions.
          22                 : #if defined(__i386__)
          23                 : #define cpuid(a, b, c, d, inp) \
          24                 :   asm ("mov %%ebx, %%edi\n"    \
          25                 :        "cpuid\n"               \
          26                 :        "xchg %%edi, %%ebx\n"   \
          27                 :        : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
          28                 : #elif defined (__x86_64__)
          29                 : #define cpuid(a, b, c, d, inp) \
          30                 :   asm ("mov %%rbx, %%rdi\n"    \
          31                 :        "cpuid\n"               \
          32                 :        "xchg %%rdi, %%rbx\n"   \
          33                 :        : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
          34                 : #endif
          35                 :
          36                 : #if defined(cpuid)        // initialize the struct only on x86
          37                 :
          38                 : // Set the flags so that code will run correctly and conservatively, so even
          39                 : // if we haven't been initialized yet, we're probably single threaded, and our
          40                 : // default values should hopefully be pretty safe.
          41                 : struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
          42                 :   false,          // bug can't exist before process spawns multiple threads
          43                 :   false,          // no SSE2
          44                 : };
          45                 :
          46                 : // Initialize the AtomicOps_Internalx86CPUFeatures struct.
          47            1464 : static void AtomicOps_Internalx86CPUFeaturesInit() {
          48                 :   uint32 eax;
          49                 :   uint32 ebx;
          50                 :   uint32 ecx;
          51                 :   uint32 edx;
          52                 :
          53                 :   // Get vendor string (issue CPUID with eax = 0)
          54            1464 :   cpuid(eax, ebx, ecx, edx, 0);
          55                 :   char vendor[13];
          56            1464 :   memcpy(vendor, &ebx, 4);
          57            1464 :   memcpy(vendor + 4, &edx, 4);
          58            1464 :   memcpy(vendor + 8, &ecx, 4);
          59            1464 :   vendor[12] = 0;
          60                 :
          61                 :   // get feature flags in ecx/edx, and family/model in eax
          62            1464 :   cpuid(eax, ebx, ecx, edx, 1);
          63                 :
          64            1464 :   int family = (eax >> 8) & 0xf;        // family and model fields
          65            1464 :   int model = (eax >> 4) & 0xf;
          66            1464 :   if (family == 0xf) {                  // use extended family and model fields
          67               0 :     family += (eax >> 20) & 0xff;
          68               0 :     model += ((eax >> 16) & 0xf) << 4;
          69                 :   }
          70                 :
          71                 :   // Opteron Rev E has a bug in which on very rare occasions a locked
          72                 :   // instruction doesn't act as a read-acquire barrier if followed by a
          73                 :   // non-locked read-modify-write instruction.  Rev F has this bug in
          74                 :   // pre-release versions, but not in versions released to customers,
          75                 :   // so we test only for Rev E, which is family 15, model 32..63 inclusive.
          76            1464 :   if (strcmp(vendor, "AuthenticAMD") == 0 &&       // AMD
          77                 :       family == 15 &&
          78                 :       32 <= model && model <= 63) {
          79               0 :     AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
          80                 :   } else {
          81            1464 :     AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
          82                 :   }
          83                 :
          84                 :   // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
          85            1464 :   AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
          86            1464 : }
          87                 :
          88                 : namespace {
          89                 :
          90                 : class AtomicOpsx86Initializer {
          91                 :  public:
          92            1464 :   AtomicOpsx86Initializer() {
          93            1464 :     AtomicOps_Internalx86CPUFeaturesInit();
          94            1464 :   }
          95                 : };
          96                 :
          97                 : // A global to get use initialized on startup via static initialization :/
          98            1464 : AtomicOpsx86Initializer g_initer;
          99                 :
         100            4392 : }  // namespace
         101                 :
         102                 : #endif  // if x86
         103                 :
         104                 : #endif  // ifdef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_

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